1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, in particular, to integrated circuits that include both circuit elements wherein a silicide is formed and circuit elements wherein no silicide is formed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which form an electric circuit. Circuit elements provided in integrated circuits can include active devices, such as, for example, field effect transistors and/or bipolar transistors. Additionally, integrated circuits can include passive devices, such as capacitors, inductivities and/or resistors.
In field effect transistors, a gate electrode as well as source, drain and channel regions formed in a semiconductor material are provided. The gate electrode may be separated from the channel region by a gate insulation layer providing electrical insulation between the gate electrode and the channel region. Adjacent the channel region, the source region and the drain region that are doped differently than the channel region are provided. Depending on an electric voltage applied to the gate electrode, the field effect transistor may be switched between an ON-state and an OFF-state, wherein an electric conductivity of the channel region in the ON-state is greater than an electric conductivity of the channel region in the OFF-state.
For increasing the conductivity of the channel region of a field effect transistor in the ON-state, it has been proposed to provide an elastic stress in the channel region. A tensile stress may increase the mobility of electrons in a semiconductor material such as silicon. Providing a tensile stress in the channel region of an N-channel transistor may help to improve the conductivity of the channel region, so that a greater current through the channel region in the ON-state of the transistor can be obtained. A compressive stress in a semiconductor material such as silicon may improve the mobility of holes, so that providing a compressive stress in the channel region of a P-channel transistor may help to obtain a greater current through the channel region of the P-channel transistor in the ON-state of the transistor.
Techniques for providing an elastic stress in the channel region of a field effect transistor include stress memorization techniques. The source and drain regions are amorphized by an ion implantation, and a layer of a dielectric material having an intrinsic stress, for example a layer of stressed silicon nitride, is deposited over the semiconductor structure wherein the transistor is provided. Then, an annealing process is performed in the presence of the dielectric layer. During the annealing process, the amorphized source and drain regions are re-crystallized, wherein a crystalline structure that is influenced by the stress provided by the dielectric layer is obtained. Distances between atoms in the re-crystallized source and drain regions of the transistor may deviate from the natural crystal lattice constant of the semiconductor material wherein the source and drain region are formed, so that an intrinsic elastic stress is obtained in the source region and the drain region. The intrinsic elastic stress of the source region and the drain region may be maintained at least partially after a removal of the stressed dielectric layer that may be performed in later processing steps.
Types of resistors that may be provided in integrated circuits include resistors that include an elongated line providing an electrical resistance, the elongated line being formed from one or more material layers that are deposited on a surface of a semiconductor structure from which the integrated circuit will be formed. For reducing the number of material layers that are deposited and/or patterned in the formation of an integrated circuit, it has been proposed to use material layers that are deposited for forming gate electrodes of field effect transistors also for forming resistors.
Gate electrodes of field effect transistors may include polysilicon. In addition to polysilicon, in transistors formed in accordance with the high-k metal gate technique, one or more metal layers may be provided in the gate electrode for adjusting the work function of the gate electrode.
For improving an electric conductivity of gate electrodes of field effect transistors, a silicide may be formed from the polysilicon of the gate electrodes. This may be done by depositing a metal layer over the semiconductor structure and then performing an annealing process to initiate a chemical reaction wherein a silicide is formed from the polysilicon and the metal.
A formation of silicide in elongated lines of resistors may be disadvantageous, in particular, if resistors having a relatively high resistance are to be provided, since, in contrast to gate electrodes of field effect transistors, in elongated lines of resistors, a high resistivity of the material of the elongated lines may be desirable.
Therefore, before depositing a metal layer that is employed for the formation of silicide in the gate electrodes of field effect transistors, a hardmask may be formed over the resistors. The hardmask can prevent a contact between the metal and the polysilicon of the elongated lines of the resistors, so that no silicide is formed in the elongated lines of the resistors.
An issue associated with the above-described techniques for forming field effect transistors and resistors in integrated circuits is that a relatively large number of processes of depositing and patterning material layers may be required, which can increase the complexity of and time required for the manufacturing process. Moreover, in etch processes used for patterning material layers, damages of features formed in earlier stages of the manufacturing process may occur.
The present disclosure provides methods wherein the above-mentioned issue may be avoided or at least reduced.